It is a major problem to be solved with a bipolar transistor to improve a high frequency characteristic and assure a sufficiently high breakdown voltage. But, in order to improve the high frequency characteristic, it is of vital interest to thin the base. When the base is formed according to an ion implantation process, since an impurity profile presents a Gaussian distribution, it is necessary to thicken the base in order to prevent punch through between a collector and an emitter. Further, the ion implantation process suffers from a number of problems caused by, for example, channeling, dispersions due to the reduction of energy, damages caused by implantation and the like, which poses a limit to achieving ultra thinning of the base.
In recent scholarly circles, a bipolar transistor having a base layer formed by epitaxial process has been published as an alternative to the base structure formed by the conventional ion implantation process. If the epitaxial process is used, since the impurity profile exhibits a stepwise form, even if the base is made thinner than when it is formed according to the ionimplantation process, the punch through breakdown voltage between the collector and the emitter can be assured high. Further, since the thickness of the base and the impurity density can be controlled with excellent accuracy, an extremely thin and properly dense base layer can be formed.
A conventional example of the self-aligned type bipolar transistor having a base formed by the epitaxial process is hereinafter described with reference to one published in Technical Digest of IEDM90, pp. 607-610. In this structure, the base layer is formed with an epitaxial layer selectively grown on a silicon substrate, and constitutes a self-aligned type bipolar transistor utilizing the most state-of-the-art technique. FIGS. 1A through 1E are respectively a cross-sectional view illustrating a manufacturing process of the transistor.
As illustrated in FIG. 1A, after an n.sup.+ -type embedded layer 2 is formed on a p-type silicon substrate 1, an n-type collector layer 3 is epitaxially grown thereon and an oxide film 4 for separating elements from each other is formed on the n-type collector layer 3. Thereafter, an n.sup.+ -type collector area 5 is formed, and an oxide film 6, p.sup.+ -type base polysilicon electrode 7 and a nitride film 8a are formed.
Subsequently, as shown in FIG. 1B, a first sidewall 9a comprising a nitride film is formed on an aperture of the nitride film 8a and p.sup.+ -type base polysilicon electrode 7.
Next, as shown in FIG. 1C, the oxide film 6 is etched to a predetermined degree according to isotropic wet etching. At this time, a space surrounded by the n-type collector layer 3, p.sup.+ -type base polysilicon electrode 7 and oxide film 6 is formed.
Subsequently, as shown in FIG. 1D, a p-type base layer 10 is formed on the n-type collector layer 3, which is exposed by etching the oxide film 6, by utilizing the selective epitaxial process. Simultaneously, the p-type base layer 10 and the p.sup.+ -type base polysilicon electrode 7 are interconnected by a p-type polysilicon film 11 grown from the polysilicon electrode 7.
Next, as shown in FIG. 1E, a second sidewall 12 comprising an oxide film is formed and, subsequently, an n.sup.+ -type emitter polysilicon electrode 13 is formed and, then, a heat treatment is conducted to form an n.sup.+ -type emitter layer 14.
In the foregoing transistor structure, the area of the p-type base layer 10 is determined according to the amount of the oxide film 6 to be etched. When the oxide film 6 is retrograded by 0.1 to 0.3 .mu.m from the aperture of the p.sup.+ -type polysilicon electrode 7, since the interconnecting area between the p-type base layer 10 and the p.sup.+ -type base polysilicon electrode 7 can be set to 0.1 to 0.3 .mu.m, the area of the p-type base layer 10 can be made extremely small.
In this conventional example, the oxide film 6 sandwiched between the p.sup.+ -type base polysilicon electrode 7 and the n-type collector layer 3 remains. This is because a margin is necessary between the distance by which the oxide film 6 is to be retrograded by wet etching and the distance ranging from the oxide film 4 for separating the elements up to the aperture end of the p.sup.+ -type base polysilicon electrode 7. That is, it is necessary to form the aperture of the p.sup.+ -type base polysilicon electrode 7 in alignment with the oxide film 4 for separating the elements, and if the distance between the oxide film 4 and the aperture of the p.sup.+ -type base polysilicon electrode 7 is the same as that by which the oxide film 6 is to be retrograded and there is any misalignment therebetween, then even the oxide film 4 will be etched, at which time, as shown in FIG. 2, in the space 15 produced by etching the oxide film 4, since the p-type base layer 10 and the p.sup.+ -type base polysilicon electrode 7 cannot be interconnected, a need to allow for a margin for compensating the misalignment therein arises.
FIG. 3 illustrates a plan view of a base area according to the conventional example. Assuming that the aperture size be 0.5.times.2.0 .mu.m.sup.2, the distance by which the oxide film 6 be to be retrograded 0.2 mm, and the margin between the oxide film 4 and the aperture of the p.sup.+ -type base polysilicon electrode 7 be 0.3 .mu.m, 0.3 .mu.m in width of the oxide film 6 corresponding to this margin is left between the p-type base layer 10 and the oxide film 4. Assuring that the thickness of the oxide film 6 be 100 nm, a capacitance of about 0.8 fF is applied as the parasitic capacitance between the p.sup.+ -type base polysilicon electrode 7 and the n-type collector layer 3. Since the junction capacitance between the p-type base layer 10 and the n-type collector layer 3 is on the order of 2.5 through 4 fF, the above parasitic capacitance will rise the total base capacitance by as much as 20 through 32%.
Further, this conventional example has suffered from a problem that the base resistance becomes great because the area of the interconnecting portion between the p-type base layer 10 and the p.sup.+ -type base polysilicon electrode 7 is no more than theamount by which the oxide film 6 is to be retrograded by etching. If the distance by which the oxide film 6 is retrograded by etching is set to more than 0.2 .mu.m in order to reduce the base resistance, then, as shown in FIG. 4, voids 16 are likely to occur. This is due to the fact that the growth reaction slows down because the lateral surface comprises an oxide film at the innermost portion of a cavity portion formed by etching the oxide film 6. That is, the foregoing solution cannot reduce the base resistance.